Not Applicable
The present invention relates generally to data encoding and more specifically, to physical coding and decoding techniques for segregating and reliably communicating data over a plurality of serial channels.
In recent years there has been an increasing desire to produce electronic products which operate at ever increasing speeds. Of particular note in this regard are telecommunications devices such as routers, bridges and switches. While typical communication line rates for such devices were 10 megabits per second (mbps) for Ethernet transmissions less than a decade ago, 100 mbps Ethernet line rates have now become commonplace. Moreover, devices are currently being deployed which support ten gigabit per second (gbps) Ethernet line rates.
Data is typically received at an input port of a telecommunications device over a high speed serial communications link. Received data is converted to a parallel word format in accordance with a specified media access control (MAC) protocol for processing within the device. The width of the parallel data output from the MAC protocol is typically specified for the respective MAC protocol. A 10 gigabit per second Ethernet protocol has been described having a MAC output using a 64 bit wide data word. At such high data rates, the transport of data within the device can be problematic.
While data can be transported through the device as a parallel word to achieve workable clock rates, such is undesirable for a number of reasons. First, wide bus widths consume substantial space on the printed circuit boards for the numerous conductive paths which are required. Second, passing large numbers of conductive signals through backplanes requires large numbers of connector contacts as well as drivers and receivers. Often, it is undesirable to provide for the large number of connector contacts that are required to accommodate a 64 bit wide or greater width parallel bus. Additionally, it is recognized that interconnections through backplane connectors contribute to system unreliability and for this reason as well it is preferable to minimize the number of signal paths through backplanes and connectors. Finally, numerous integrated circuits are required in terms of drivers and receivers to interface to wide parallel buses.
In order to minimize the number of printed circuit board runs and backplane connections, parallel data has been segregated into narrower parallel data words and the respective words have been serialized for transmission over a plurality of serial channels. This technique can result in the introduction of near end and far end crosstalk in adjacent channels that can introduce data errors in the transmission. Furthermore, complex techniques and/or substantial overhead in terms of signal bandwidth and circuitry have typically been necessary to accomplish synchronization and/or framing in such systems.
Moreover, it is desirable to be able for the receive logic to be able to be acquire synchronization of serially transmitted data xe2x80x9cblindxe2x80x9d; i.e. without the use of additional synchronization signal lines since the transport of separate synchronization signals also adds to the number of printed circuit board runs and connector contacts that are needed.
It would therefore be desirable to have a data coding, decoding and transport technique which allows the transmission of data reliably through a telecommunications device without employing wide parallel buses and which permits blind acquisition of synchronization at the receiver and reassembly of the transmitted data words.
In accordance with the present invention, a method and apparatus for transporting data reliably over a plurality of serial channels is disclosed. Physical coding sublayer logic receives a parallel data word from a system interface. The parallel data word includes data of a first data channel and a monitor channel. The monitor channel is employed to convey supervisory or other information in a second data channel that is independent of the data conveyed in the first data channel. A monitor channel and the parallel data data word are applied to an error correction code generator and a error correction code (ECC) is generated. The parallel data word is divided into a plurality of lesser width data words. Selected bits of the ECC code and the monitor channel are appended to the lesser width parallel data words in a predetermined manner to form a plurality of extended lesser width parallel data words corresponding in number to the number of lesser width parallel data words. The extended lesser width parallel data words are serialized in respective serializers and transmitted over a plurality of serial data links.
Each serial channel also includes two parity bits. The first parity bit is employed for error detection and correction and additionally carries control state information. The parity bits are generated such that proper parity is indicated if the XOR sum of all bits within a channel (including the first and second parity bits) equals 1. This property is used to obtain proper word framing at receive logic within the physical coding sublayer. The second parity bit in each channel is generated such that the XOR sum of all of the second parity bits equals 0 when the channels are properly aligned. Proper word framing and alignment is verified by testing framing and alignment over a predetermined number of word samples.